The present invention relates to circuit designs for semiconductor integrated circuits, and more particularly relates to a technique for performing simulation of circuit characteristics on the basis of information for fabrication process.
In recent years, due to miniaturization of the fabrication process, influences of process variations on circuit characteristics have been increased in circuit design for semiconductor integrated circuits.
Conventionally, as a technique for a simulation of circuit characteristics, a technique in which shape parameters and the like for transistors constituting a semiconductor integrated circuit are intentionally distributed at random by the Monte Carlo simulation to estimate circuit characteristics for the semiconductor integrated circuit has been known.
Moreover, for example, Japanese Laid-Open Publication No. 2002-279012 discloses a technique in which circuit simulation of characteristics is performed by estimating, when timing analysis for a semiconductor integrated circuit is performed, a delay variation for a semiconductor integrated circuit at high speed with consideration of a delay variation for each logic cell constituting the semiconductor integrated circuit and the correlation between delay variations of the logic cells.
However, when the present inventor examined influences of process variations on circuit characteristics, it was found that shapes and characteristics of devices, interconnects and the like of a semiconductor integrated circuit are changed depending on positions of the elements and the like. In the simulations of circuit characteristics using the above-described known technique and the technique described in the Japanese Laid-Open Publication No. 2002-279012, circuit characteristics were not estimated with consideration of arrangement positions where elements of a semiconductor integrated circuit were arranged.
Moreover, when a plurality of parameters are intentionally distributed at random by the Monte Carlo simulation, an enormous calculation processing time is required.